1. Field of the Invention
The present invention relates to a test technique for a semiconductor device.
2. Description of the Related Art
In order to test a semiconductor device at low cost, a BIST (Built-In Self Test) circuit is employed. The BIST circuit thus employed provides diagnosis of defective portions and a quality check by writing and reading a defined input/output signal at a low speed to/from a device under test (which will be referred to as a “DUT” hereafter) without involving high-cost semiconductor automatic test equipment (which will be referred to as “ATE” hereafter). In particular, with regard to BISTs for memory circuits and logic circuits, many actual results and research results have accumulated. BISTs for such circuits have been implemented in production tests. The standard IEEE1149.1 was formulated by the JTAG (Joint Test Action Group) in 1990. This standard integrates the method for the boundary scan test and the input/output signals necessary for the boundary scan test. The JTAG standard (which is also simply referred to as “JTAG”) provides specifications which employ 5-bit input/output signals, i.e., the test data input TDI, the test data output TDO, the test clock TCK, the test mode select TMS, the test reset TRST (option), used for accessing the BIST circuit included in the DUT in the form of a built-in circuit, thereby providing a boundary scan test.
In many cases, the boundary scan test performed in the BIST for memory or a logic circuit is a method in which multiple flip-flops or latches provided at a circuit boundary are connected in series in the form of a daisy chain so as to write and read data. Specifically, serial data is input at a low speed via a test data input port, the data held by a flip-flop or a latch at a boundary is serially read in a given state of the DUT, and the data thus read out is compared with an expected value. Accordingly, in a case in which only the boundary scan test is performed, a small-scale apparatus or an electronic calculator (computer) having a 5-bit parallel I/O port is sufficient as a resource for the JTAG signals.
However, in many cases, in order to ensure the quality of the DUT, there is a need to perform a DC test and an input leak test, in addition to the BIST test. No test system has been proposed without involving ATE throughout all of its steps. Accordingly, some input/output ports of the ATE for performing the DC test etc., are assigned to the JTAG ports (which are also referred to as “test access ports TAP”) of the DUT. With such an arrangement, both the BIST test and the DC test are executed using a single ATE. In general, ATE devices that are capable of inputting/outputting signals at a high speed is costly according to the signal input/output speed, leading to increased test cost. Accordingly, in a case in which devices are shipped with only a basic quality guarantee, a low-cost ATE is sufficient, which generates only a low-speed signal. Currently, BIST-optimized BIST testers and so on are available.
The effectiveness of the BIST has been sufficiently proven with respect to logic circuits and memory circuits. Accordingly, there have been attempts to expand the use of the BIST to include a function of testing an analog circuit, and to provide an integrated BIST for a digital-analog mixed LSI (Large Scale Integration). There are already many research results with regard to the loopback test, which is a test in the BIST method for testing a high-speed I/F circuit which is a kind of analog circuit block. The loopback test has been implemented in production tests. Also, in the future, a BIST for an interface circuit between a digital block and an analog block, such as an A/D converter, D/A converter, etc., and a BIST for a front-end or a back-end of a wireless communication LSI, will be put to practical use.
In view of such situations, in the near future, it will be possible to provide multiple kinds of BISTs for a single DUT such as a SoC (System On a Chip) or SiP (System in a Package) on which memory circuits, logic circuits, analog circuits, A/D converters, D/A converters, high-speed I/F circuits are monolithically mounted. Improved microfabrication of the semiconductor process allows the increased circuit area (overhead) for the BIST circuit to be ignored. This permits the test items provided by the BIST to be increased. Accordingly, more BIST circuits will be mounted. Furthermore, the advantages of the BIST include a function of checking the internal circuit state of the DUT, which cannot be observed via an external port. This provides very effective information for defect analysis and for improving yield with respect to SoC devices integrally including multiple functions.
In such circumstances, as a result of examining DUTs having multiple BIST functions, the inventors have come to recognize the following problems.
1. In a case in which there are multiple BISTs according to respective control specifications independent of one another, there are differences in the control commands and the expected value comparison procedure among the BIST circuits, leading to a complicated control operation of the ATE for the BISTs provided by the DUT. This leads to increased test time and redundant test resources.
2. In a case in which the BIST circuits perform operations linked together or synchronized with one another, there is a need for the ATE to access each BIST circuit at the same time. Such an arrangement requires independent external access ports (TAPs) in increments of BIST circuits. This reduces the number of ports which can be assigned to the functions and operations of the DUT which are to be performed in the normal mode.
3. In the future, it is possible that there will be a need to provide multiple BISTs and a normal test (test in which the ATE accesses the normal input/output ports of the DUT) linked together or synchronized with one another. The current method does not support the linkage of the BISTs and the normal test, i.e., such a test cannot be performed.